About Project MEKOPP:

The aim of project MEKOPP is to scale-up photonic chip production by streamlining chip testing and fabrication validation methods. Photonic integrated circuit (PIC) production can be categorized into three major operations: chip fabrication, chip testing, and packaging. Chip fabrication is done in cleanrooms, where batches of wafers are processed together using the same steps. Chip testing verifies that the production steps resulted in the expected structures on the chip. The goal is to achieve a high-yield fabrication run, meaning that a high fraction of chips (or dice) are produced as expected. Packaging involves the adding of inputs, outputs, interconnections, additional chips, and housing to the fabricated dies. While the fabrication of photonic dies is easily scalable due to these wafer-scale production processes, the testing of the dies remain a largely manual operation. PICs contain waveguides, through which optical signals must be passed to test their propagation properties, and electronically triggered tuners and actuators, which must be tested to ensure the correct manipulation of the propagating signal. Each wafer typically contains several of these chips, and testing cannot begin until they are diced into individual dies and packaged with photonic inputs and outputs and electronic interconnections. 80% of chip production costs are in the packaging step, meaning that most of the production cost is paid upfront before the yield of a fabrication run is known. Moreover, current testing technologies are limited in terms of automation, the number of functions that can be tested at once (test density) and the speed at which to test these functions (test throughput). A fully packaged chip with fabrication defects which are only diagnosed at testing is a total waste in terms of materials, time, and energy.